This invention relates to semiconductor memories; and more particularly to random access dynamic storage memories. In the prior art, two basic types of random access dynamic storage memory cells exist. One of those cells is called the "single level poly cell"; and the other cell is called a "double level poly cell".
A single level poly cell is comprised of a semiconductor substrate having an insulating layer on one surface thereof. Lying on this insulating layer are two spaced apart conductors. One of the conductors defines the charge storage region of the cell; whereas the other conductor defines the charge transfer channel of the cell.
The single level poly cell is relatively simple to fabricate; however, a problem with that cell is that it occupies too much chip space. This is due to the spacing that exists between the two conductors. The minimum width to which this spacing can be fabricated is limited by the minimum line width that can be produced. And using presently available photolithography technology that is suitable for mass production, this minimum line width is 3.+-.1/2 microns.
By comparison, a double level poly cell occupies less space; but it is more difficult to fabricate. In a typical process, the cell is fabricated by first forming an insulating layer on one surface of a semiconductor substrate. Then, a conductive layer is formed on the insulating layer. The conductive layer and insulating layer are then selectively removed in a self-aligned fashion to define a conductor over the charge storage region of the cell.
Next, a second insulating layer is grown over the entire surface of the above structure. This insulating layer grows at one rate over the bare semiconductor substrate, and at another rate (which is approximately 1.6 times faster) over the conductor in the storage region.
Then a second conductive layer is formed on the second insulating layer. This second conductive layer is subsequently patterned to cover the charge transfer channel portion of the cell and also extend into the charge storage region over the first conductive plate.
Due to the overlap between the first and second conductors, a parasitic capacitance is formed. The size of this capacitance varies inversely with the thickness of the insulating layer which separates the two conductors. Thus, it is desirable to make that insulating layer relatively thick, such as 3,000 .ANG.-4,000 .ANG. for example. Such a thickness would also minimize the probabilty of shorts occurring between the first and second conductive layers.
However by comparison, it is desirable to have the thickness of the insulating layer which underlies the conductor in the charge transfer region to be relatively thin. This will allow charge to flow more quickly through the charge transfer channel with the application of a voltage to the overlying conductor. Preferably, the thickness of the insulating layer in that region is only 300 .ANG.-500 .ANG..
Unfortunately, the above described conventional fabrication process does not allow for the two desired insulating layer thicknesses to be achieved. If the insulating layer over the charge transfer channel is made to equal 400 .ANG., then the insulating layer which separates the two conductors will only be about 1.6 times 400 .ANG.. This is substantially less than the desired 3,000 .ANG.-4,000 .ANG.. Conversely, if the insulating layer over the storage region is made to equal the desired 3,000 .ANG.-4,000 .ANG., then the thickness of the insulating layer over the charge transfer channel will be too thick.
Also described in the prior art, is a particular version of the double level poly cell which has special relevance here. This particular double level poly cell is known as the "high capacity memory cell". It is described in U.S. Pat. No. 4,125,993 issued Nov. 21, 1978 to inventors Baldwin et al.
Basically, that cell incorporates a shallow dopant layer and a deep dopant layer throughout the charge storage region of the substrate to increase the capacitance per unit area of that region. Such an increase is of course desirable since it enables the size of the charge storage region to be reduced for a given amount of charge storage capacity. However, an unattractive aspect of the teachings of that patent is the manner in which the charge storage region and charge transfer channel are interconnected. In particular, that connection is made in the conventional single level poly and/or double level poly manner as described above.
Therefore, it is a primary object of this invention to provide an improved high capacity memory cell wherein the charge storage region and charge transfer channel are interconnected in a novel fashion which enables the cell to occupy minimal space and simultaneously minimize parasitic capacitance and catastrophic shorts between the conductors of the cell.